1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a double spacer and a method of making the same to enhance the reliability of the semiconductor device.
2. Discussion of Related Art
The miniaturization of devices according to a scaling rule is used in a semiconductor device to achieve large-scale integration and high-speed operation. In MOS devices, this leads to a decrease in the threshold voltage due to shortening of the channel. Also, the effect of a depleted layer upon the channel in a source/drain region is reduced so as to attain a stable threshold voltage in the semiconductor device. To meet the requirements such as large-scale integration and high operational speed, semiconductor devices generally have a pocket implantation region or a thin junction layer formed by a rapid heat treatment to increase the concentration of dopants in a localized region of the substrate.
FIGS. 1-3 contain schematic cross-sectional diagrams illustrating a method of fabricating a prior art semiconductor device. In the prior art device illustrated in FIGS. 1-3, a device separating region 12 is formed in a p-type silicon substrate 10 by a known LOCOS step. As shown in FIG. 1, a gate oxide layer 14 is formed on the upper surface of the active region of a silicon substrate 10, and a conductive layer is formed on the gate oxide layer 14. The conductive layer is subjected to photolithographic and etching steps to form a gate electrode 16. A buffer oxide layer 18 is deposited on the the gate electrode 16 by an oxidation step. Using the buffer oxide layer 18 as a mask, arsenic (As) is typically lightly implanted as an n-type impurity to form a lightly doped LDD region 20 which self aligns at the edge of the gate electrode 16 in the vicinity of the surface of the silicon substrate 10.
Referring to FIG. 2, an oxide layer is then formed on the structure as an insulating layer. The structure is then subjected to a back-etching step to form a spacer 22 on the sidewalls of the gate electrode 16.
As shown in FIG. 3, using the spacer 22 as a mask, boron (B) is implanted as a p-type impurity in a medium concentration and at the same time arsenic (As) is heavily implanted as an n-type impurity. This results in a B-doped pocket implantation region 24 and an As-doped source/drain region 26 which self-align at the edge of the spacer 22 in the vicinity of the surface of the silicon substrate 10. The resulting product is then subjected to a rapid heat treatment step so that the pocket implantation region 24 has a shape surrounding the source/drain region 26.
One drawback to this prior art approach is that the semiconductor device is generally subjected to a very rapid heat treatment at high temperature for a short time in order to form a thin junction. This makes it very difficult to diffuse dopants of the pocket implantation region 24 in a controlled fashion to a desired depth, i.e., under the source/drain region 26. This can result in device reliability problems and reduced device performance.